This invention relates to semiconductor transistors, and more particularly, to a vertical pass transistor having a gate with dual work function materials for use in Dynamic Random-Access Memory (DRAM) cell applications.
DRAM pass transistors require off-state leakage current of less than 1 fA per cell to achieve an adequate retention time. The scaling of channel length requires higher channel doping to control short channel effect and sub-threshold leakage. Increasing channel doping results in a degraded retention time due to junction leakage. These and other constraints present a challenge when designing planar pass transistor at below 100 nm node, as described in an article by J. Mandelman et al., “Challenges and future directions for the scaling of dynamic random-access memory (DRAM),” IBM Journal of Research and Development, Vol. 46, (2002), pp.187-213. A vertical pass transistor coupled to a deep trench capacitor cell design is an alternative for continuous scaling of DRAM technology because the channel length of the pass transistor is decoupled from the minimum feature size or the DRAM cell size. Doping of the vertical channel can be achieved by ion implant through the sacrificial oxide before the array top oxide and the wordline stack deposition.
FIG. 1 illustrates a conventional vertical pass transistor DRAM cell. Shown therein is a vertical pass transistor positioned above the deep trench capacitor. The pass transistor is connected to the storage node of the capacitor by an N+ diffusion region, referred to as buried strap. The gate of the pass transistor is made of a single work function material, usually N+ doped polysilicon. The gate material of the transistor is isolated from the conductor within the deep trench capacitor by a trench top oxide. A thick collar oxide separates the buried strap N+diffusion region from the N+ doped buried plate. The gate material at the top part of the deep trench is surrounded by a nitride spacer.
Several components of the leakage as seen by the storage node diffusion are:
1) Sub-Threshold Leakage:
To retain a logic “1” when the wordline and bitline are both at ground requires that the MOSFET threshold voltage (Vt) be at least 0.8V. The threshold voltage is provided by the following equation:Vt=φm−φs−Qox/Cox+2ψB+(4εsiqNaψB)1/2/Cox   (1)wherein φm and φs are work functions of the material forming the gate and of the silicon substrate. Qox represents the charge in the gate dielectric, and Cox is the gate dielectric capacitance. ψB is the difference of potential between Fermi's level and the intrinsic Fermi level. Na is the doping concentration in the channel.
In prior art DRAM technology, N+ doped polysilicon must be used as the gate material and P-type doped silicon is required for the channel. The work function of the N+ polysilicon is approximately 4.05V, and the work function of the P-type doped silicon is:φs=4.05+0.56+ψB.   (2)Therefore,φm−φs=0.56+ψB   (3)
With N+ polysilicon used as gate material, a high channel doping must be used to achieve a high Vt while the high channel doping can lead to high junction leakage, low carrier mobility and high back bias sensitivity. The latter two effects degrade the write back current.
Another approach to prevent a sub-threshold leakage is to place the wordline at a negative voltage when a “1” is retained in the storage node, and the bit line is at zero volts while the negative wordline-low increases the GIDL current.
2) Junction Leakage.
The junction leakage between the diffusion region and the channel limits the channel doping.
3) Gate Induced Drain Leakage (GIDL).
GIDL current in the diffusion regions limits the use of negative wordlines. Therefore, it becomes a challenge to prevent the three previously mentioned leakages and still maintain an appropriate write back current. A solution to the above challenge is to engineer the channel, as described, e.g., by K. MacStay et al., in the article “Vertical Pass Transistor Design for Sub-100 nm DRAM Technologies” , Symposium on VLSI Technology Digest of Technical Papers, p. 180, 2002. McStay selects the channel doping to have a peak concentration at the top of the channel near the bit line diffusion. Thus, the Vt adjustment implant and the doping near the storage node are partially decoupled. There are still others disadvantages regarding this method. First, there remains a large body effect for the device which degrades the write back current. Second, the Vt adjustment implant cannot be totally decoupled from the doping near the storage node as a result of the diffusion of the channel dopant being boron.
To reduce the body effect and improve the write back current, an angled Vt implant into the deep trench side-wall is used to generate a non-uniform doping in a lateral direction. The doping concentration near the surface of the side-wall is high while the Vt and channel doping away from the surface of the channel is low, which reduces the body effect and improves the write back current. The difficulty of this design is that Vt of the device is highly sensitive to the deep trench top recess depth which, from a process point of view, is difficult to control.
A negative wordline low is effective in reducing the channel doping while keeping the sub-threshold leakage low. While the negative wordline voltage causes a large gate induced drain leakage (GIDL) current and degrades the retention performance, having a negative wordline voltage in a DRAM pass gate is not possible.